A standard top-gate OFET is formed by depositing a layer of semiconductor followed by a layer of dielectric on conductive source/drain electrodes. A conductive layer is then deposited on top of the dielectric between the source and drain electrodes to form an OFET structure. Two important determinants of OFET performance are: (1) the semiconductor layer must be deposited between the source and drain electrodes, but must minimize the overlap over the source and drain electrodes, and (2) the dielectric should be as thin as possible without resulting in short circuits.
One problem with the standard fabrication method described above, particularly with respect to the top-gate OFET structure, is that the semiconductor ink tends to flow far beyond the edge of the source and drain electrodes, causing the semiconductor layer to extend beyond desirable boundaries, thereby introducing undesired capacitance between the gate and the drain. This increased capacitance is responsible for significant loss of transistor switching speed, thereby causing circuits built with this structure to run more slowly. Another problem with the above OFET structure is that, when making the dielectric layer thin to increase transistor performance, there is an increased probability of shorting between the gate and the source/drain through pinholes in the dielectric, created in large measure by non-uniform ink flow of the dielectric.
What is desired, therefore, is a novel OFET structure in which at least the boundaries of the ink in the dielectric layer are tightly controlled to substantially improve switching speeds and to reduce pinhole shorting associated with the prior art structures.